An information handling system (IHS) may include a processor integrated circuit (IC) for processing, handling, communicating or otherwise manipulating information. Modern IHSs often include integrated circuits (ICs) that incorporate several components integrated together on a common semiconductor die. Some IHSs operate as test systems or test managers that evaluate the functionality and performance characteristics of IC designs during the development process of the IC design. A device under test (DUT) is another name for an IC design on which a test system conducts tests.
During operation, ICs may experience hard errors or soft errors. Hard errors are IC faults that persist over time. For example, an IC may experience a short circuit or an open circuit that does not go away with time. In contrast, a soft error is an error that may occur once and then not recur over time. For example, a cosmic ray or alpha particle may pass through a latch in the IC and cause the latch to change state or “flip”. Noise in a circuit adjacent the IC may also cause a soft error.
Unfortunately, soft error rate (SER) is increasing in today's ICs due to higher device density in these ICs. Lower IC operating voltage also makes an IC more susceptible to soft errors, thus causing higher SER than in the past. Arrays within ICs, such as memory and caches, are susceptible to soft errors. Combinatorial logic within ICs is also susceptible to soft errors. A conventional way to deal with increasing SER in memory arrays is to employ error correction code (ECC) memory and scrubbing. However, increasing SER in the logic and data flow paths of ICs is a more complex problem. One approach is to employ redundancy in the logic to decrease or correct for SER. However, redundancy is a difficult and costly solution.
It is frequently hard to determine the SER of an IC or system of ICs. One way to perform an SER determination is to actually fabricate the IC or IC system. After fabrication of the IC system, specialized test apparatus may bombard the IC system with cosmic rays and alpha particles in a laboratory environment to create faults or errors. Test apparatus measures the SER of the IC system while bombardment continues. Unfortunately, this approach requires completion of the IC design and fabrication of the actual hardware of the IC system prior to testing. This approach undesirably limits the amount of controllability and observability of the IC design during experimentation.
Another way to determine SER effects is by fault injection into a software simulation or software model of a particular IC design. Unfortunately, this software simulation model approach may be very slow. The size of the software model is also typically limited such that the software model may include just a portion of the IC design rather than the entire IC design when the IC is very large.
It is desirable to provide a method and apparatus for causing soft errors in an IC design that addresses the problems above without actually fabricating the IC design in semiconductor form.